One type of prior nonvolatile integrated circuit memory is the erasable programmable read-only memory ("EPROM"). EPROMs frequently use memory cells that have electrically isolated gates (floating gates) such as an enhancement-type n-channel metal-oxide semiconductor field effect transistor (MOSFET) with two gates made of polysilicon material. One of the gates in this enhancement-type-n-channel MOSFET is not electrically connected to any other part of the circuit (e.g. a floating gate) and the other gate in this enhancement-type n-channel MOSFET functions in the same manner as the gate of a regular enhancement MOSFET (Adel S. Sedra and Kenneth C. Smith, "Microelectronics Circuits", CBS College Publishing, 1982, pp. 776-780). The EPROM stores information in the memory cells in the form of charge on the floating gates and is programmed by placing a charge on the floating gates. The EPROM can be programmed by a user, and once programmed, the EPROM retains its data until erased. Other memory devices such as a Flash Electrically Erasable Programmable Read Only Memory ("EEPROM") are also user programmable. Flash EEPROMs are also programmed by electrically injecting a charge onto the floating gates.
The EPROM comprises memory cells logically organized by rows and columns which form a memory array. Typically, the rows represent word lines and the columns represent bit lines. Furthermore, the EPROM has a column decoder for decoding the appropriate bit lines and a row decoder for decoding the appropriate word lines of each individual memory cell selected to be either programmed or read.
Typically, during programming, the user provides the appropriate voltage signals at the input/output pins of the device to select the rows and columns of the memory cells selected to be programmed. Furthermore, the user applies a high voltage signal (approximately 13 volts) at the programming input Vpp which generates a programming current that flows through each selected bit line to increase the drain voltage of each selected memory cell, thereby accelerating electrons through the channel of the selected memory cell.
Simultaneously, the programming voltage generates another programming current that passes through each selected word line to increase the voltage at the control gate of each selected memory cell, thereby establishing an electric field in the insulating oxide of the selected memory cell. This electric field attracts the hot electrons and accelerates them toward the floating gate. In this way, the floating gate is charged, and the charge that accumulates on it becomes trapped, thus programming each selected memory cell.
During a reading operation, the user also provides the appropriate voltage signals at the input/output pins of the device to select the rows and columns of the desired memory cells in which data is to be read from. Thus, during a reading operation, a voltage (in some embodiments approximately Vcc) is applied to the word line of each selected row. The memory cells that are not programmed will conduct heavily, thus lowering the voltage of its bit line. On the other hand, a programmed cell will not conduct and its bit line remains at a high voltage (if the bit lines are precharged to high voltages). The column decoder selects at least one of the bit lines and connects it a sense amplifier which, in turn, detects the change in voltage of the bit line and thus determines whether the stored bit is a "1" or a "0". Typically, a programmed memory cell stores a "1" and an unprogrammed memory cell stores a "0".
Thus, in order to effectively program or read a memory cell, the appropriate voltage level must be applied over the word line and bit line to the selected memory cell. Typically, about 13 volts is applied to the gates of the memory cells and about 6.5 v is applied to the drains of the memory cells selected during a programming operation. A voltage of about Vcc is applied to the gates of the memory cells and about 1.5 v is applied to the drain of the memory cells selected during a reading operation. Furthermore, when a memory cell is not selected (e.g. deselected) for either a reading operation or a programming operation, Vss is applied over the bit line or word line.
Therefore, a high voltage switch provides a conductive pathway for the current generated from the programming input Vpp to flow from the programming input Vpp onto the selected lines during a programming operation, thus, increasing the voltage on the selected lines to the voltage level necessary to program the memory cells. During programming, the high voltage switch also isolates the current generated from the programming input Vpp from the deselected lines, thus, preventing the programming current from increasing the voltage on the deselected lines. However, during a reading operation, the high voltage switch is bypassed altogether such that the voltage on the lines is not affected by the voltage provided at the programming input Vpp.
Typically, a programmable memory device performs reading operations much more frequently than the programming operations. For example, a programmable memory device may be programmed once or twice before being placed in a system, and once installed in the system the programmable memory device may perform reading operations continually. Therefore, it is desirable to reduce the DC power consumption of the programmable memory device by reducing the leakage current during a reading operation.
The high voltage switch design in the prior art provides a current leakage path through each high voltage switch coupled to a deselected line. Therefore, as the number of deselected lines increases (which occurs whenever the number of memory cells on an IC increases), the overall leakage current of the programmable memory device increases. In other words, the larger the memory array in the prior art programmable memory device, the more DC power the device consumes. For example, each deselected line in a particular 1 Megabit EPROM device draws approximately 30 micro amps of leakage current from VCC to VSS. Since the number of deselected lines in a high density EPROM (e.g. greater than one Megabit) is greater than 1000 lines, the leakage current through the high voltage switches is at least 32 milli amps.
Therefore, as denser programmable memory devices (having more memory cells on an IC) are designed, it is desirable to reduce the amount of leakage current flowing through the high voltage switches while maintaining the functionality of each high voltage switch. The present invention provides a high voltage switch (HVS) design that performs high voltage-charge up and high voltage isolation during a programming operation while providing the capability of significantly reducing the overall DC power consumption through the HVSs during a reading operation. For example, the leakage current may be reduced from approximately 32 milli amps to approximately 3.25 milli amps in a particular (1 Megabit) EPROM device. Therefore, by providing low power high voltage switches that reduce the total leakage current during a reading operation, the power consumption of the memory circuit is minimized.